Maswali yanayounganishwa na mwongozo · Kati Kiwango

Maswali ya AI katika Upangaji wa sakafu ya Chip na Maswali ya Usanifu

Gundua uwekaji wa chipu uliojifunza, kwa grafu za orodha ya wavu, makro zinazofuatana, malengo ya seva mbadala, uwekaji wa seli-msingi, uwezekano, na hesabu za HPWL.

Njia za mwongozo zinazohusianaAI Katika Upangaji wa sakafu ya Chip na Ubunifu
Swali 1 ya 8

What physical decision does chip floorplanning or placement make?

Hakiki kila swali8 maswali

Majibu na maelezo huonekana unapojibu maswali.

  1. What physical decision does chip floorplanning or placement make?
    • Only the chip’s retail selling price
    • Only its package color
    • Only the company name on the box
    • Where circuit components occupy locations on the chip canvas
  2. How should the cited paper’s report of competitive floorplans produced in hours be interpreted?
    • As a result for its studied setup, netlists and comparisons
    • As proof that every chip can be fully signed off in the same time
    • As a guarantee of global optimality for all circuits
    • As an architecture-independent law about every design tool
  3. Je, AI inawekaje tatizo la uwekaji?
    • Kama nadhani ya risasi moja
    • Kama uamuzi mfuatano: weka kizuizi kimoja, angalia, kisha weka kinachofuata
    • Kama kichocheo cha kupikia
    • Kama aina ya lahajedwali
  4. Je! ni 'orodha gani' ambayo mtandao wa neural wa grafu hujifunza kutoka?
    • Orodha ya nywila za mtandao
    • Muundo wa wavu wa uvuvi
    • Grafu ya vipengele na jinsi vinavyounganishwa
    • Jedwali la uelekezaji wa mtandao
  5. Which fast objective signals are documented by the cited Circuit Training project?
    • Proxy wirelength, congestion and density
    • A proof of all manufacturing and timing requirements
    • Only the product’s market price
    • Only a mandatory social-media popularity score
  6. In Google’s cited 2020 method description, what places standard-cell clusters after the RL macro placements?
    • Only an unchanged alphabetical component sort
    • Only a user-interface screenshot
    • A guarantee that no standard cells remain
    • A force-directed procedure
  7. For pins at (0,0),(4,0),(4,3), what is the half-perimeter wirelength estimate in coordinate units?
    • 14
    • 12
    • 7
    • 4
  8. What does the documented can_place_node check evaluate for a proposed grid location?
    • Whether the entire chip is globally optimal
    • Whether the node can be placed there under relevant location constraints
    • Whether every final routed timing path passes signoff
    • Whether the model’s prediction is a factual-confidence probability