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Synopsys and TSMC have announced a deepened partnership aimed at streamlining the design and manufacturing of advanced AI and high-performance computing (HPC) systems. The collaboration focuses on integrating agentic AI capabilities into electronic design automation (EDA) flows, supporting TSMC’s A14 process technology, and enhancing multi-die design through TSMC’s 3DFabric and CoWoS packaging technologies.
Synopsys has achieved A14 certification across its digital and analog design flows, enabling customers to begin utilizing TSMC’s latest process technology. This includes new device routing enablement for analog place-and-route automation, intended to increase layout productivity.
The partnership introduces agentic AI workflows designed to automate complex tasks. Specifically, Synopsys’s Custom Compiler is being used for analog migration, while Fusion Compiler now incorporates LLM-assisted analysis to improve design productivity. A new agentic AI chiplet floorplan co-optimization flow has also been added to the 3DIC Compiler platform to support TSMC’s 3DFabric technology.
The companies are collaborating on power delivery and connectivity for multi-die designs. This includes support for integrated voltage regulators (IVRs) on TSMC’s CoWoS packaging and an integrated design flow for co-packaged optics (CPO) using TSMC’s COUPE technology.
Synopsys has expanded its silicon-proven IP portfolio for TSMC’s N2P and N3P processes, including tape-outs for PCIe 7.0, HBM4, and 224G Ethernet PHY. These components are designed to provide the high-bandwidth connectivity required for modern AI workloads.
Kildedetaljer: prnewswire.com ↗
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As AI hardware demands grow in complexity, the ability to automate the design process is becoming critical for maintaining performance and energy efficiency. By agentic AI into EDA tools like Fusion Compiler and 3DIC Compiler, Synopsys aims to reduce the manual burden on engineers, potentially shortening the time-to-market for complex AI chips. This partnership provides a standardized, certified pathway for designers to utilize TSMC’s most advanced nodes, such as A14 and N2P, which are essential for the next generation of data center and edge AI hardware.
The semiconductor industry is facing a 'complexity wall' where the number of transistors and the intricacy of multi-die architectures make traditional manual design methods increasingly unsustainable.
By shifting toward agentic AI—systems capable of autonomous decision-making within defined design parameters—Synopsys and TSMC are attempting to automate the 'design convergence' process, which is the time-consuming phase of ensuring a chip meets all performance, power, and area (PPA) requirements.
The inclusion of silicon-proven IP for advanced standards like HBM4 and UCIe ensures that designers can integrate these critical components into their AI systems with lower risk, as the IP has already been validated on TSMC’s manufacturing processes.
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Industry observers should monitor the actual adoption rates of these agentic design flows among semiconductor manufacturers. While the tools are certified for TSMC’s latest nodes, the practical impact on design cycle times and the reliability of agentic automation in complex multi-die environments remain to be proven in large-scale commercial production. Additionally, the integration of co-packaged optics (CPO) on TSMC’s COUPE technology will be a key indicator of how effectively these companies can address the connectivity bottlenecks in future AI systems.
The effectiveness of 'agentic' automation in real-world, high-stakes chip design environments. While the companies claim increased productivity, the industry will be watching to see if these tools reduce the frequency of design iterations or 'respins' required before mass production.
The rollout of TSMC’s A14 and N2P processes. The success of this partnership depends on the availability and yield of these advanced nodes, which are currently the frontier of semiconductor manufacturing.
The adoption of co-packaged optics (CPO). As AI clusters grow, electrical interconnects are becoming a bottleneck; the success of the Synopsys-TSMC flow for COUPE technology could signal a shift in how high-speed data is moved within future AI systems.