quiz bu lëkkale ak tegtal · Diggante Niveau

IA ci Chip Planioŋ ak Design Quiz

Saytu plasement chip biñ jàng, ak graphique netlist, macro yu toppalante, mébetu proxy, plasement selil buñ miin, mëna dem, ak arithmétique HPWL.

Yooni njiit yu jëm ciIA Ci Planifikaasioŋ ak Design Chip
Laaj 1 de 8

What physical decision does chip floorplanning or placement make?

Xoolaatal laaj bu nekk8 laaj

Sooy def quiz bi, tontu yi ak leeral yi dañuy feeñ.

  1. What physical decision does chip floorplanning or placement make?
    • Only the chip’s retail selling price
    • Only its package color
    • Only the company name on the box
    • Where circuit components occupy locations on the chip canvas
  2. How should the cited paper’s report of competitive floorplans produced in hours be interpreted?
    • As a result for its studied setup, netlists and comparisons
    • As proof that every chip can be fully signed off in the same time
    • As a guarantee of global optimality for all circuits
    • As an architecture-independent law about every design tool
  3. naka la IA di defaree jafe-jafe plasement bi?
    • Benn xalaat
    • Ni dogal bu toppalante: def benn blok, seetlu, ba noppi def beneen bi
    • Ni rëset togg
    • Ni ñuy tànnee këyitu xayma
  4. Lan mooy 'netlist' bi reso neuronal graphique di jàngee ci?
    • Limu baatu-jàll reso bi
    • Design mbaal ngir napp
    • Graafiku komponent yi ak ni ñu leen di boolee
    • Tablo biy wane yoon wi ci internet
  5. Which fast objective signals are documented by the cited Circuit Training project?
    • Proxy wirelength, congestion and density
    • A proof of all manufacturing and timing requirements
    • Only the product’s market price
    • Only a mandatory social-media popularity score
  6. In Google’s cited 2020 method description, what places standard-cell clusters after the RL macro placements?
    • Only an unchanged alphabetical component sort
    • Only a user-interface screenshot
    • A guarantee that no standard cells remain
    • A force-directed procedure
  7. For pins at (0,0),(4,0),(4,3), what is the half-perimeter wirelength estimate in coordinate units?
    • 14
    • 12
    • 7
    • 4
  8. What does the documented can_place_node check evaluate for a proposed grid location?
    • Whether the entire chip is globally optimal
    • Whether the node can be placed there under relevant location constraints
    • Whether every final routed timing path passes signoff
    • Whether the model’s prediction is a factual-confidence probability