quiz bu lëkkale ak tegtal · Diggante Niveau

Laajte ci sistemu serebral

Dafay leeral mboolem ci echelu wafer, jokkoo ci kaw wafer, redondance, ak ay leeral ci produit WSE-3 ak CS-4.

Yooni njiit yu jëm ciSistemu serebral
Laaj 1 de 8

Lan moo wuute ci jëmmal motëru eskaalu wafer bu Cerebras?

Xoolaatal laaj bu nekk8 laaj

Sooy def quiz bi, tontu yi ak leeral yi dañuy feeñ.

  1. Lan moo wuute ci jëmmal motëru eskaalu wafer bu Cerebras?
    • Dafay nuru benn processeur buñ tabax ci kaw benn wafer silisium bu mat sëkk
    • Mooy puce IA bi gëna ndaw ci àdduna bi
    • Dafay dox te amul kuuraŋ
    • Plastik lañu ko defaree, du silisium
  2. Lan moo waral denc core yépp ci benn wafer dimbali IA ci performance?
    • Dina tax chip bi gëna xéewale ci yobbu
    • Done yi dañuy jaar ci kaw fiil yu gaaw yi ci puce bi, du ci reso bu yeex bi ci biti
    • Dina tax doo soxla benn losisel
    • Dafay may puce bi mu féey ci biir ndox
  3. Lu tollu ci ñaata tranzistor la WSE-3 am?
    • Lu tollu ci 4 junni
    • Lu tollu ci 4 milioŋ
    • Lu tollu ci 4 bilioŋ
    • Lu tollu ci 4 téemeeri
  4. What is one Cerebras system-level capability advertised for its CS-4 rack-scale system?
    • It uses only a single CPU and no AI accelerator
    • It replaces every model with a database
    • It guarantees the same speedup on every workload
    • It combines multiple wafer-scale processors in a rack-scale platform
  5. naka la ko Cerebras di def su amee ay jafe-jafe ci defar puce bu rëy nii?
    • Dafay jëfandikoo core yu bari ak routing ngir wër barab yu defoon
    • Dafay sànni bépp wafer ak bépp sikk
    • Du bàyyi xel ci ay sikk, di yónnee chips yu yàqu
    • Dafay defar transistor bu nekk ak loxoom
  6. What are the WSE-3 specifications Cerebras reports in its product materials?
    • Four billion transistors and 900 cores
    • Four trillion transistors and about 900,000 AI-optimized cores
    • One thousand transistors and one million CPU sockets
    • A fixed count of parameters for every model
  7. How can a wafer-scale processor route around manufacturing defects?
    • Assume every fabricated core is perfect
    • Move all computation to a hard drive
    • Use redundant cores and routing so defective regions can be bypassed
    • Rebuild the silicon after deployment
  8. Why can on-wafer memory and communication benefit some AI workloads?
    • They eliminate every computation bottleneck
    • They make all models fit in one core
    • They guarantee lower latency for every task
    • They can reduce data movement between separately packaged processors and memory