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Cadence has announced an expanded partnership with TSMC to provide advanced design capabilities for AI and high-performance computing (HPC) chips. The collaboration includes the certification of Cadence’s digital, signoff, and custom/analog design tools for TSMC’s A14 and A16 process technologies. Additionally, the companies are enabling agentic AI chip design flows and expanded support for TSMC’s 3DFabric technology, which allows for the integration of hundreds of chiplets in wafer-scale systems.
Cadence’s digital full flow, including the Innovus Implementation System and Cerebrus Intelligent Chip Explorer, is now certified for TSMC’s A16 and A14 processes. For custom and analog design, the Virtuoso Studio suite now supports automated design migration to these nodes, which Cadence claims can reduce design iterations by up to 2.5 times.
On the IP front, Cadence has taped out UCIe-64G on the A14 process, with LPDDR6 IP currently in development. For the N2P process, Cadence has certified its analog, digital, and signoff flows, with DDR5, LPDDR5, and PCIe 6.0 IP already taped out.
The partnership also extends to advanced packaging, specifically supporting TSMC’s SoW-X (System-on-Wafer) design flow. This enables the design of systems with hundreds of chiplets and millions of bumps, utilizing the Integrity 3D-IC platform for system planning. Additionally, the companies have enabled integration for TSMC-COUPE (Compact Universal Photonic Engine) with Cadence’s 224G SerDes IP to support high-bandwidth connectivity.
Awọn alaye orisun: hpcwire.com ↗
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This partnership is critical for the semiconductor industry as it directly addresses the increasing complexity of designing AI accelerators and hyperscale systems. By certifying design tools for TSMC's most advanced nodes (A14, A16, N2P), Cadence provides chip designers with the necessary infrastructure to improve power, performance, and area (PPA) metrics. The integration of agentic AI design flows and advanced 3D-IC packaging support helps reduce development cycles and schedule risks for companies building the next generation of AI hardware. As AI models grow in size and demand more , the ability to efficiently design and manufacture complex, multi-chiplet systems becomes a primary bottleneck that this collaboration aims to resolve.
The semiconductor industry is currently facing a 'complexity wall' where the design of AI-specific chips requires managing billions of transistors and intricate 3D-IC architectures. By providing silicon-proven IP and certified design flows, Cadence reduces the 'schedule risk' for companies like Global Unichip Corp. (GUC), which rely on these tools to deliver custom silicon for hyperscale systems. The shift toward agentic AI design flows represents a move toward automating the most labor-intensive parts of the chip design process, potentially allowing engineers to focus on higher-level architectural decisions. This collaboration ensures that the foundational software tools keep pace with the rapid evolution of TSMC’s manufacturing nodes, which is essential for maintaining the performance trajectory of AI infrastructure.
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Industry observers should monitor the Q4 2026 availability of Artisan Foundation IP and mixed-signal IP for the A14 process, as these are essential for developers beginning their design cycles. Furthermore, the adoption rate of the newly certified agentic AI design flows among major semiconductor manufacturers will be a key indicator of how quickly these tools can reduce design iterations and improve time-to-market for AI-specific silicon. The performance of the TSMC-COUPE photonic engine integration with Cadence’s 224G SerDes IP in real-world HPC applications remains a significant technical milestone to track.
The primary unknown remains the specific performance gains individual customers will realize when transitioning to the A14 and A16 nodes using these new flows, as real-world results often differ from theoretical benchmarks. Additionally, while Cadence has announced the development of various IP blocks, the actual yield and stability of these components in early-stage production will be critical for the success of the first wave of A14-based AI chips. The market will also be watching to see how competitors respond to the integration of agentic AI flows, as this could set a new standard for design automation in the semiconductor sector.