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Tech Times reports that Reno-based Positron AI closed an $875 million Series C financing round at a $5 billion post-money valuation. The funding is intended to support Asimov, a custom ASIC targeted for tapeout by the end of 2026 and production in the second half of 2027. The design uses LPDDR5X memory rather than the HBM used in leading Nvidia accelerators.
Tech Times reports that Positron’s financing came in two tranches: a $375 million Series C at a reported $3.5 billion pre-money valuation and a Series C-1 of up to $500 million. The outlet says investors included NEA, Andra Capital, Atreides Management, Valor Equity Partners, SemiAnalysis Capital, the Qatar Investment Authority, Cisco Investments and others. The report says Positron plans to use the capital for Asimov and related engineering infrastructure.
According to Tech Times, Asimov is designed to use LPDDR5X, a commodity memory type used in smartphones and laptops, instead of HBM. The company claims its architecture could achieve more than 90% memory-bandwidth utilization, while the report says Positron characterizes typical GPU decode utilization as below 30%. Those figures are attributed to Positron and are not independently confirmed. Tech Times also reports that Positron’s Atlas system is deployed in more than 50 Oracle Cloud Infrastructure racks and is used by the Parasail inference service, with Jump Trading and i3d.net identified as production customers. The source does not establish general availability or pricing.
Szczegóły źródła: techtimes.com ↗
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The financing highlights a consequential hardware dispute over how AI should be optimized. Positron argues that sequential model decoding often uses only a fraction of an accelerator’s theoretical memory bandwidth, making effective utilization, memory capacity and supply-chain availability more important than peak bandwidth alone. If the company’s claims hold, its approach could offer lower-cost and more widely deployable inference infrastructure. However, Tech Times’ account makes clear that Asimov has not taped out and that its performance figures remain company design targets, not independent measurements.
Tech Times frames the round as a bet on -specific hardware at a time when AI systems are increasingly run continuously for users rather than only trained. The report says Positron’s design targets between 288 gigabytes and 2,304 gigabytes of memory per Asimov chip, with additional capacity possible through CXL expansion, and says Titan is intended to serve models exceeding 16 trillion parameters. These are planned specifications, not demonstrated capabilities.
The supply-chain argument is also significant. The source says HBM depends on specialized manufacturing and advanced packaging, while LPDDR5X is produced by multiple suppliers at larger commodity scale. That could matter to buyers constrained by memory availability, rack power or cooling requirements. Tech Times reports that Titan is being designed for both air- and liquid-cooled facilities, but no independent total-cost, throughput or efficiency result is provided.
The central caveat is validation. The source cites earlier third-party commentary that Positron’s Atlas comparisons with Nvidia systems require verification, and says Asimov has not yet taped out. Tech Times also reports a substantially lower realizable-bandwidth estimate for Asimov than the peak bandwidth of Nvidia’s future Rubin architecture. The outcome therefore remains unresolved.
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The key tests are Asimov’s tapeout, independent benchmarks, production availability and the economics of Titan systems built from Asimov chips. Access terms, customer eligibility and pricing for Asimov and Titan are not documented in the source. Positron’s current Atlas deployments provide operating experience, but they do not independently validate Asimov’s future performance claims.
Watch for Asimov’s reported late-2026 tapeout, working silicon and independent tests across different model sizes, context lengths and decode workloads. The most useful measures will be tokens per dollar, tokens per watt, usable memory capacity and sustained throughput rather than peak specifications alone.
Watch whether the reported Atlas deployments expand beyond the current customers and whether Positron offers a clear procurement path for enterprises. The source does not document public purchase terms, cloud access, service pricing or a general release date for Asimov or Titan.
Also watch whether LPDDR5X supply and packaging advantages translate into reliable production at scale. The source presents Positron’s roadmap and investor support as evidence of confidence, but neither establishes that the future ASIC will match HBM-based systems in real-world performance or economics.