What happened
Google announced the completion of the 32-bit Coral NPU architecture by releasing the Matrix Execution Unit (Milestone 4). The company made the complete 32-bit RTL available on GitHub and released the v1.0 foundation of its open-source MLIR/IREE compiler toolchain. Additionally, Google detailed a partnership with Synaptics to launch three commercial hardware products based on this standard, including the Coralboard SR and SL, at Synaptics Tech Day on October 20, 2026.
Google Research announced the completion of the 32-bit Coral NPU architecture with the release of the Matrix Execution Unit, designated as Milestone 4. This unit leverages the RISC-V VME specification to handle 2D matrix-matrix and matrix-vector multiplications, which are critical for modern ML workloads like attention layers. The dedicated outer-product multiply-accumulate engine computes 256 MACs per cycle, allowing for quadratic throughput scaling and configurable performance up to 1 TOPS within a sub-10 mW power envelope.
To support this hardware, Google released the complete 32-bit RTL on GitHub and the v1.0 foundation of its open-source MLIR/IREE compiler toolchain. This toolchain supports models from JAX, PyTorch, and TensorFlow via standard representations like StableHLO and TOSA. It handles workload partitioning between the host CPU and the Coral NPU, operator fusion, and matrix tiling for local SRAM. The release also includes an open-source MPACT simulator and reference FPGA design to allow teams to models before silicon fabrication.
Google highlighted a collaboration with Synaptics, which is launching three commercial silicon and hardware products built on Coral NPU technology at Synaptics Tech Day on October 20, 2026. These products include the Coralboard SR and Coralboard SL, developed with hardware partner Grinn. The Coralboard SR targets milliwatt-class wearables, while the Coralboard SL targets 1 TOPS boards. Both use the same compiler foundation, allowing ML teams to optimize a model once and deploy it across different power budgets without splitting the software workflow.
The announcement also details partnerships with VeriSilicon for design implementation and verification, and GlobalFoundries for the 12LP+ FinFET process. GlobalFoundries reported that this process accelerates core timing by 70% and reduces standard-cell area by up to 15% across RTL iterations. Google stated that the next phase of the roadmap includes a 64-bit Coral NPU architecture and CHERI support for security.
Source details: developers.googleblog.com ↗
Why it matters
This release addresses the fragmentation of edge AI hardware by providing an open, RISC-V-based standard that allows developers to optimize models once and deploy them across different silicon vendors. By including a dedicated matrix engine capable of 1 TOPS in a sub-10 mW envelope, the architecture enables complex multimodal workloads, such as running compact models like Gemma, on battery-powered devices without relying on the cloud. This reduces the 'fragmentation tax' of rewriting kernels for proprietary chips and lowers the barrier to entry for custom edge SoC design.
Edge AI development has historically been hindered by a 'fragmentation tax,' where developers must rewrite kernels and debug vendor-specific compilers for every proprietary chip architecture. By providing an open hardware and software standard based on RISC-V, Google aims to unify the edge ecosystem, allowing for portable, energy-viable intelligence that can run on diverse devices from wearables to industrial robots.
The inclusion of a dedicated Matrix Execution Unit is significant because it addresses the energy inefficiency of running 2D matrix math on 1D vector engines. By reusing weights and activations in local registers, the architecture enables continuous, multimodal workloads on small batteries. This allows for practical applications such as real-time voice translation on wearables, spatial audio filtering, and low-latency visual perception on robots, which were previously limited to simple tasks like keyword spotting due to power constraints.
The release of the RTL and compiler toolchain lowers the barrier for silicon teams to bring custom edge SoCs to production. By providing a turnkey path from model to silicon, including simulation and FPGA reference designs, Google is positioning Coral NPU as a foundational standard for the next generation of , potentially reducing reliance on cloud round-trips for latency-sensitive and privacy-critical applications.
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What to watch next
Monitor the commercial availability and pricing of the Synaptics Coralboard SR and SL hardware. Watch for the adoption of the Coral NPU standard by other silicon vendors beyond Synaptics and GlobalFoundries. Track the development of the announced 64-bit architecture and CHERI security support, which are planned for the next phase of the roadmap.
The commercial launch of the Synaptics Coralboard SR and SL products on October 20, 2026, will be a key indicator of the standard's market adoption. The availability, pricing, and developer reception of these devkits will determine how quickly the ecosystem can move from prototyping to production.
Adoption by other silicon vendors and foundries beyond the announced partners (VeriSilicon, GlobalFoundries, Synaptics, Grinn) will be crucial for the Coral NPU to become a true industry standard. Wider adoption would further reduce the fragmentation tax for ML developers.
The development of the 64-bit Coral NPU architecture and CHERI security support, mentioned as the next phase of the roadmap, will be important for addressing more complex workloads and security concerns in edge deployments. The timeline for these releases is not specified in the source.