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Intel details GPU D-series and rack designs for agentic AI

Pulse 2.0 reports that Intel unveiled specifications for its GPU D-series inference accelerator and new Xeon-based rack designs at the Open Compute Project Global Summit.

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Source-page capture accompanying Intel details GPU D-series and rack designs for agentic AI
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pulse2.com
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Key terms

Memory (Agent Memory)
Stored context an AI agent uses across steps or sessions to improve continuity.
Inference
The runtime phase where a trained model generates predictions or outputs.
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Finding relevant documents or records from a knowledge source for a query.
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What happened

Pulse 2.0 reports that Intel introduced technical details for its GPU D-series accelerator, formerly code-named Crescent Island, alongside Xeon-based rack designs and open software initiatives for large-scale agentic AI infrastructure. Intel says the accelerator can provide up to 480 GB of LPDDR5X memory, 1.5 TB per second of bandwidth and 1.3 petaflops of FP8 compute within a 350-watt power envelope. Pricing, release timing and general availability were not reported.

Pulse 2.0 reports that Intel made the announcements at the Open Compute Project Global Summit as part of a strategy centered on heterogeneous infrastructure for agentic AI. Intel described agentic workloads as involving multiple stages, including , reasoning, orchestration, tool use and execution, which can place simultaneous demands on compute, memory, power and cost.

According to the report, the Intel GPU D-series is based on the company's Xe3P architecture and is designed for sustained, memory-intensive . Intel says it supports up to 480 GB of LPDDR5X memory, 1.5 TB per second of memory bandwidth and 1.3 petaflops of FP8 compute at a 350-watt power envelope. Intel also says one card can support models of up to 300 billion parameters, while an eight-GPU configuration can support more than one trillion parameters.

Intel said the accelerator uses a standard PCIe form factor and air cooling, which the company presents as a way to fit it into existing data-center environments. Pulse 2.0 also reports that Intel introduced Xeon-based rack designs developed with ecosystem partners. Select Xeon 6+ configurations can scale beyond 46,000 CPU cores per rack at approximately 133.45 kilowatts of total rack power, according to Intel.

The company is pairing the hardware with a common Xe software foundation, support for AI frameworks and tools, and an AI for Enterprise Agent Toolkit already optimized for Xeon. The report says Intel is working with OEMs, ODMs, neocloud providers, software vendors and AI-native companies on validated systems. These claims come from Intel as reported by Pulse 2.0 and were not independently confirmed in the supplied source.

Source details: pulse2.com ↗

Why it matters

The announcement addresses a practical infrastructure problem: agentic AI workloads may require repeated , , orchestration and tool use rather than a single model response. Intel is proposing a mix of CPUs, GPUs, open software and standards-based rack designs. If the reported specifications and integration claims hold in independent testing, enterprises could have another option for memory-intensive inference without immediately redesigning their data centers. The report does not establish real-world performance, customer adoption or commercial availability.

Agentic systems can make several model calls and coordinate external tools during one task, making memory capacity, data movement, orchestration and operating cost important alongside raw accelerator speed. Intel's proposed CPU-and-GPU approach is aimed directly at that infrastructure challenge.

The reported PCIe and air-cooled design could be practically relevant for organizations seeking to add capacity to existing facilities. However, the source does not show that the D-series works in a particular customer's environment or that it avoids all specialized infrastructure requirements.

Intel's emphasis on common software, open standards and Day 0 support for emerging open models reflects an effort to reduce deployment friction across changing AI workloads. The source does not provide independent software compatibility tests, performance benchmarks or evidence of production-scale deployments.

There is no reported price, shipping date, purchasing channel or confirmed availability. The reported specifications are company claims, and no independent results are provided for latency, throughput, energy efficiency, reliability or total cost of ownership.

Interactive Mechanism

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Thinking Budget (Test-Time Tokens):1,024 tokens
Complex Accuracy79%Math & Code Logic
Latency3.2sTime to first full output
Inference Cost$0.0092Per query estimated
Reasoning StyleStep VerificationInternal chain depth
Active Thinking Trace:
1Deconstruct user problem into formal constraints
2Propose candidate hypotheses & step-by-step calculation
3Self-correction: Backtrack and refute subtle edge cases
4Exhaustive consistency check & final output synthesis
Core takeaway: Test-time compute fundamentally changes AI economics. Instead of only scaling during pre-training, giving reasoning models more tokens at inference time allows them to systematically solve PhD-level STEM problems.
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What to watch next

The key unknowns are when the GPU D-series will ship, how much it will cost, and whether independent benchmarks validate Intel's performance, power and model-capacity claims. Watch also for announced OEM, ODM, neocloud and software-platform deployments, as well as progress on Open Compute Project accelerator standards.

A commercial launch date, regional availability, pricing and named purchasing options would clarify who can actually use the GPU D-series and under what conditions.

Independent testing should show how the accelerator performs on long-context, concurrent and multi-tenant workloads, including performance per watt and per dollar.

Customer and partner deployments would help establish whether the reported rack designs and software stack move beyond validated reference platforms into production systems.

The Open Compute Project's Open Adapter Card workgroup and Intel's other standards contributions may indicate whether the proposed interoperability benefits become broadly usable across vendors.

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