Cerebras Systems Quiz

Answers and explanations appear as you take the quiz.

1. What is unusual about the design of the Cerebras Wafer-Scale Engine?
   • It is an entire processor built on a single full silicon wafer
   • It is the world's smallest AI chip
   • It runs entirely without electricity
   • It is made of plastic instead of silicon
2. Why does keeping all the cores on one wafer help AI performance?
   • It makes the chip cheaper to ship
   • Data moves over fast on-chip wires instead of slow external networking
   • It eliminates the need for any software
   • It allows the chip to float in liquid
3. Roughly how many transistors does the WSE-3 contain?
   • About 4 thousand
   • About 4 million
   • About 4 trillion
   • About 4 hundred
4. What is one Cerebras system-level capability advertised for its CS-4 rack-scale system?
   • It uses only a single CPU and no AI accelerator
   • It replaces every model with a database
   • It guarantees the same speedup on every workload
   • It combines multiple wafer-scale processors in a rack-scale platform
5. How does Cerebras deal with manufacturing defects on such a huge chip?
   • It uses redundant cores and routing to work around defective spots
   • It throws away every wafer with any flaw
   • It ignores defects and ships broken chips
   • It manually repairs each transistor by hand
6. What are the WSE-3 specifications Cerebras reports in its product materials?
   • Four billion transistors and 900 cores
   • Four trillion transistors and about 900,000 AI-optimized cores
   • One thousand transistors and one million CPU sockets
   • A fixed count of parameters for every model
7. How can a wafer-scale processor route around manufacturing defects?
   • Assume every fabricated core is perfect
   • Move all computation to a hard drive
   • Use redundant cores and routing so defective regions can be bypassed
   • Rebuild the silicon after deployment
8. Why can on-wafer memory and communication benefit some AI workloads?
   • They eliminate every computation bottleneck
   • They make all models fit in one core
   • They guarantee lower latency for every task
   • They can reduce data movement between separately packaged processors and memory