Guide-linked quiz · Hard Level

CUDA and GPU Programming Quiz

Check core CUDA concepts, including kernels, SIMT execution, memory access, shared memory, and higher-level GPU programming tools.

Related guide pathsCuda And GPU Programming
Question 1 of 8

In CUDA terminology, what is a 'kernel'?

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  1. In CUDA terminology, what is a 'kernel'?
    • A function run in parallel by many GPU threads
    • The core of an operating system
    • A type of memory chip
    • The GPU's cooling system
  2. What does the SIMT execution model mean?
    • Slow Input, Many Transfers
    • Single Instruction, Multiple Threads run the same instruction on different data
    • Single Image, Multiple Textures
    • Sequential Instructions, Manual Timing
  3. Why do PyTorch and TensorFlow rarely require users to write raw CUDA?
    • GPUs cannot run user code
    • CUDA is illegal to use directly
    • They call optimized CUDA libraries like cuDNN and cuBLAS internally
    • They only run on CPUs
  4. What is 'warp divergence' and why does it hurt performance?
    • A networking error that drops packets
    • The GPU physically bending under heat
    • A bug that deletes memory
    • Threads in a warp take different branches and must run serially
  5. Why is 'coalesced' memory access important in CUDA?
    • Adjacent threads reading adjacent addresses is far more efficient
    • It encrypts data automatically
    • It frees up disk space
    • It disables the GPU fans
  6. What is OpenAI Triton in relation to CUDA programming?
    • A CUDA driver that replaces NVIDIA GPUs
    • A Python-like language and compiler for writing efficient GPU kernels
    • A model-serving server that only loads TensorFlow checkpoints
    • A framework that converts GPUs into CPUs
  7. What does a CUDA kernel launch configuration specify?
    • A model tokenizer vocabulary
    • The number of training labels
    • The grid and block dimensions used to organize thread execution
    • The host operating system
  8. Why might a CUDA kernel use shared memory?
    • To make data available across every cluster without communication
    • To replace all registers
    • To store the model permanently on the GPU
    • To let threads in a block reuse data from a faster on-chip memory space

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