What happened
NVIDIA has introduced preview-stage configuration recipes for its AI Cluster Runtime (AICR) to support the deployment and validation of Kubernetes environments on the upcoming Vera Rubin NVL72 hardware. These recipes, part of the NVIDIA DSX AI Factory Platform, provide reproducible configurations for drivers, runtimes, and networking components required to operate the new architecture. The company successfully validated these configurations on early-access Vera Rubin hardware using GPU Operator v26.7.0 and the Dynamic Resource Allocation (DRA) driver v0.5.0, confirming end-to-end deployment and performance gating for training workloads.
NVIDIA's AI Cluster Runtime (AICR) now includes a 'Vera Rubin' recipe family, specifically targeting the NVL72 tray. These recipes are designed to automate the complex orchestration of drivers, kernels, and networking required for the new hardware. The validation process utilized an RKE2 environment on Ubuntu 26.04, confirming that the stack can be deployed and verified within hours.
The validation process included a cross-node NCCL all-reduce performance gate, ensuring that the NVLink fabric operates at the expected bandwidth. The team successfully demonstrated the injection of IMEX (Interconnect Memory Exchange) channels into pods, a critical requirement for high-performance training workloads on this architecture.
The release also highlights specific technical prerequisites, such as the requirement to disable host-managed IMEX services when using DRA-managed ComputeDomains. NVIDIA noted that these recipes are currently in a 'Preview' state, meaning they do not yet carry full production support or lifecycle qualification.
Source details: developer.nvidia.com
Why it matters
Configuring Kubernetes for high-performance AI hardware is notoriously complex, with minor misconfigurations often leading to performance bottlenecks or total system failure. By providing versioned, validated recipes, NVIDIA aims to reduce the 'Day 1' operational burden for platform teams deploying Vera Rubin clusters. This release is significant because it establishes a standardized, reproducible path for integrating new silicon into cloud-native stacks. It also highlights the practical challenges of early-silicon bring-up, such as the need for specific driver-kernel compatibility and the resolution of hardware-fabric issues, providing a blueprint for early adopters to plan their infrastructure software stacks.
The complexity of modern AI infrastructure means that even minor mismatches in software versions or configuration settings can prevent workloads from running. By capturing these configurations in reusable recipes, NVIDIA is attempting to standardize the 'bring-up' process for its most advanced hardware.
The validation of these recipes on early silicon provides a critical feedback loop. For example, the bring-up process identified an unmapped architecture value in the go-nvlib packages, which was subsequently fixed and integrated into the official DRA driver v0.5.0. This demonstrates how the AICR toolchain serves as a testing ground for the broader software ecosystem.
For organizations planning to deploy Vera Rubin, these recipes provide a concrete, verifiable baseline. They allow platform teams to understand the specific software requirements—such as the need for CUDA 13.4 for kernels—well before the hardware reaches general availability.
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What to watch next
The primary focus for users is the transition of these recipes from 'Preview' to 'Supported' status as the Vera Rubin platform approaches general availability. Additionally, users should monitor the availability of -optimized runtime images built against CUDA 13.4 or higher, which are currently required to unlock the full performance potential of the Rubin architecture. Future updates will likely address the current limitations in inference serving, where existing vLLM images lack the necessary kernel compilation support. Platform teams should also track the evolution of the DRA driver and GPU Operator as they move beyond early-silicon validation.
performance remains a key area for development. While the Rubin architecture is supported in recent vLLM versions, the necessary kernels require compilation against CUDA 13.4. Currently, published vLLM images do not meet this requirement, meaning inference performance validation is deferred until updated runtime images are available.
The 'Preview' status of these recipes means they are subject to change. NVIDIA explicitly warns that a digest check against current recipes will likely report a mismatch as the platform matures. Users should treat the current evidence as a historical record of the validation process rather than a final production configuration.
The integration of DraNet and NodeWright tuning profiles will continue to evolve. As the hardware moves toward general availability, PCI ID allocations and final driver optimizations will likely necessitate updates to the current recipe catalog.