AI in Semiconductor Fab Yield Optimization

Yield is the fraction of chips (dies) on a wafer that work. Fabs lose yield to random particles, systematic process problems and slow drift in equipment. Because a wafer can spend weeks in the fab, catching a problem days late can ruin many lots. AI helps in three main areas. First is defect detection and classification. Optical and electron-beam inspection tools find anomalies on wafers, and automatic defect classification models label them by type. Separately, electrical test produces wafer maps showing which dies failed. The spatial pattern is a clue: an edge ring suggests a problem at the wafer edge during a process like etching, while a scratch suggests handling damage. The public WM-811K dataset, drawn from real fab wafer maps, is widely used in research on classifying these patterns. Second is virtual metrology. Measuring every wafer at every step is slow and expensive, so fabs sample. Virtual metrology predicts measurement results from sensor data tools already record, such as pressure, temperature, gas flow and RF power, giving an estimate for every wafer. Third is process control. Fault detection and classification systems watch tool sensor traces for abnormal behavior, and run-to-run controllers adjust recipe settings between lots to hold results on target. Machine learning can improve both by modeling nonlinear relationships that traditional statistical process control misses. Several misconceptions are common. Fabs do not have huge labeled datasets for every defect type: rare defects may appear only a few times, classes are heavily imbalanced, and labels depend on expert engineers. Models also go stale when tools undergo maintenance or recipes change. And a prediction alone is not enough; engineers need a plausible physical cause before they change a process. This topic concerns manufacturing, not chip layout design.